sky130_fd_sc_hs__dlclkp
Clock gate
- Cell name: sky130_fd_sc_hs__dlclkp
- Type: cell
- Library: sky130_fd_sc_hs
- Inputs: 2 (GATE, CLK)
- Outputs: 1 (GCLK)
- Read the docs
Truth table
| CLK | GATE | GCLK | |||
|---|---|---|---|---|---|
| 0 | 0 | 0 | |||
| 0 | 1 | 0 | |||
| 1 | 0 | 0 | |||
| 1 | 1 | 0 |
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sky130_fd_sc_hs__dlclkp_1
-
sky130_fd_sc_hs__dlclkp_2
-
sky130_fd_sc_hs__dlclkp_4
