sky130_fd_sc_hd__clkdlybuf4s50
Clock Delay Buffer 4-stage 0.59um length inner stage gates
- Cell name: sky130_fd_sc_hd__clkdlybuf4s50
- Type: cell
- Library: sky130_fd_sc_hd
- Inputs: 1 (A)
- Outputs: 1 (X)
- Read the docs
Truth table
| A | X | |||
|---|---|---|---|---|
| 0 | 0 | |||
| 1 | 1 |
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sky130_fd_sc_hd__clkdlybuf4s50_1
-
sky130_fd_sc_hd__clkdlybuf4s50_2
