onidev

IC Simulations and Reverse-engineering.

  • Home
  • ICs
  • Contact
  • About

GF180MCU CMOS Standard Cells

gf180mcu_fd_sc_mcu9t5v0

GlobalFoundries 180nm MCU 9 track standard cells libraries.

Logic cells

INV
BUF
AND2
AND3
AND4
OR2
OR3
OR4
NAND2
NAND3
NAND4
NOR2
NOR3
NOR4
XOR2
XOR3
XNOR2
XNOR3
MUX2
addh
MUX4
addf

And-Or-Invert, Or-And-Invert cells

AOI21
AOI22
AOI211
AOI221
AOI222
OAI21
OAI22
OAI31
OAI32
OAI33
OAI211
OAI221
OAI222

D-type flip flop, D-latch, clock-gating latch cells

dffnq
dffnrnq
dffnrsnq
dffnsnq
dffq
dffrnq
dffrsnq
dffsnq
sdffq
sdffrnq
sdffrsnq
sdffsnq
latq
latrnq
latrsnq
latsnq
icgtn
icgtp

Misc

clkbuf
clkinv
bufz
invz
hold
dlya
dlyb
dlyc
dlyd
tieh
tiel
fillcap



gf180mcu_fd_sc_mcu7t5v0

GlobalFoundries 180nm MCU 7 track standard cells libraries.

Logic cells

INV
BUF
AND2
AND3
AND4
OR2
OR3
OR4
NAND2
NAND3
NAND4
NOR2
NOR3
NOR4
MUX2
MUX4
XOR2
XOR3
XNOR2
XNOR3
addh
addf

And-Or-Invert, Or-And-Invert cells

AOI21
AOI22
AOI211
AOI221
AOI222
OAI21
OAI22
OAI31
OAI32
OAI33
OAI211
OAI221
OAI222

D-type flip flop, D-latch, clock-gating latch cells

dffnq
dffnrnq
dffnrsnq
dffnsnq
dffq
dffrnq
dffrsnq
dffsnq
sdffq
sdffrnq
sdffrsnq
sdffsnq
latq
latrnq
latrsnq
latsnq
icgtn
icgtp

Misc

clkbuf
clkinv
bufz
invz
dlya
dlyd
dlyb
dlyc
fillcap
hold
tieh
tiel

Home

Copyright © Boris Marmontel