RE of the Coleco Adam MIOC chip
This reverse engineering project aims to demonstrate the capabilities of my nodal editor.
The Coleco Adam MIOC is a very small ASIC, and two die shots are available on siliconpr0n.
|NCR 8338d||NCR 8404d|
Note: you can download them here and here.
It has just one metal layer, and is arranged using standard cells in only 6 lines. The cells looks pretty simple, except a large one which appears many times.
Identifying the technology used
The NCR 8338/8404 is from 1983.
Like many circuits of this time, it should be NMOS, and more precisely NMOS depletion-load (like the Z80, MOS 6502 or Intel 8086).
We can easily differenciate between enhancement and depletion mode pull-up.
For one, the gate of the transistor is connected to VCC, and for the other, the gate is connected to the output, between the drain and the source of the two transistors.
The smallest standard cell we can find (it should be an inverter) is composed of two transistors.
To reverse a cell, the first step is to identify the inputs and the outputs:
- The inputs are always connected to the gate of one or more transistors
- The outputs are always connected to the source or the drain of one or more transistors
Here we have only 2 I/Os. We can easily say the left one is the output, and the right one the input.
The output is not connected directly to the power line, so it’s depletion load NMOS logic.
If you have trouble visualizing the layers, here is a traced version.
- Orange: polysilicon
- Green: N-type silicon
- Red: NMOS transistor
- Yellow: contacts
- Dark green: vias
Now we can easily trace the circuit in the editor.
We can also simplify the bottom transistor and replace it with a pullup resistor.
Reverse the cells
Now we can reverse the simplest cells with 2 inputs. They are pretty straightforward.
Left one is a series of two transistors, so this is a NAND.
Right one is a parallel of two transistors, this is a NOR.
Three transistors in parallel
This 3-input cell is clearly 3 transistors in parallel, so it’s a 3-NOR.
Two series in parallel
Two series in parallel constitute an AOI cell: Z = (AB+CD)
Complex 2-inputs cell
A more complex cell with two inputs and one output. With this complexity for only two inputs, it’s probably a XOR or a NXOR.
We can see two distinct networks:
- one on the left with 3 mos and a pullup
- one on the right with 2 mos in parallel and a pullup
The right network is clearly a NOR, and the left one seems to be two series in parallel with a serie of one transistor, and a serie of two transistors. So basically an AOI gate.
A NOR followed by an AOI should be an XOR gate. Let’s check by tracing the circuit.
Then let’s generate the truth table:
AB Y 00:0 01:1 10:1 11:0
Complex 4-inputs large cell
This one is the most complex gate in the IC, and it appears 15 times.
It is quite difficult to read it directly, so we start by tracing the layers.
Note: contacts at the bottom left and right are totally invisible on the pictures.
These two traces are connected to the outputs, and we are in an open drain configuration, so they must be pull-up resistors.
The only logical configuration I see is therefore the one with these contacts.
This cell is a memory and works much like a flip-flop, outputs are on the left and the right for Q and Q (or the opposite).
A stabilized state of the chip looks like this:
After some refactoring in the editor, we can see that this cell is composed of 6x 3-NOR gates and 2x INV.
Now that we have all the cells, we can just do the wiring.
Then place and connect the cells.
Here the IC in a stabilized state, with all inputs at 0.